/*
 *	ApOS (Another Project software for s3c2410)
 *	
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License version 2 as
 *	published by the Free Software Foundation.
 *			
 *
 */
#ifndef _SDI_H
#define _SDI_H

struct sdi_control_obj
{
	volatile unsigned int *sdicon;
	volatile unsigned int *sdipre;
	volatile unsigned int *sdicarg;
	volatile unsigned int *sdiccon;
	volatile unsigned int *sdicsta;
	volatile unsigned int *sdirsp0;
	volatile unsigned int *sdirsp1;
	volatile unsigned int *sdirsp2;
	volatile unsigned int *sdirsp3;
	volatile unsigned int *sdidtimer;
	volatile unsigned int *sdibsize;
	volatile unsigned int *sdidcon;
	volatile unsigned int *sdidcnt;
	volatile unsigned int *sdidsta;
	volatile unsigned int *sdifsta;
	volatile unsigned int *sdidat;
	volatile unsigned int *sdiimsk;
};
#define NOT_DETECT	0
#define DETECT		1
//about SDICON register
#define SDICON_BYTE_ORDER_OFFSET	4
#define SDICON_RCV_IO_INT_OFFSET	3
#define SDICON_RWAIT_EN_OFFSET		2
#define SDICON_FRST_OFFSET		1
#define SDICON_ENCLK_OFFSET		0
#define TYPE_A	0
#define TYPE_B	1
#define IGN 	0
#define RCV 	1
#define DISABLE 0
#define ENABLE	1
#define NORMAL 	0
#define RESET 	1

//about SDICCON register
#define SDICCON_ABORD_CMD_OFFSET 12
#define SDICCON_WITH_DATA_OFFSET 11
#define SDICCON_LONG_RSP_OFFSET  10
#define SDICCON_WAIT_RSP_OFFSET  9
#define SDICCON_CMD_START_OFFSET 8
#define SDICCON_CMD_INDEX_OFFSET 0
#define NORMAL_CMD	0
#define ABORT_CMD	1
#define NO_DATA		0
#define WITH_DATA	1
#define SRSP		0
#define LRSP		1
#define NO_RSP		0
#define WAIT_RSP	1
#define CMD_READY	0
#define CMD_START	1

//about SDICSTA register
#define SDICSTA_RSP_CRC_OFFSET	12
#define SDICSTA_CMD_SENT_OFFSET	11
#define SDICSTA_CMD_TOUT_OFFSET	10
#define SDICSTA_RSP_FIN_OFFSET	 9
#define SDICSTA_CMD_ON_OFFSET	 8
#define SDICSTA_RSP_INDEX_OFFSET 0

#define CRC_FAIL	1
#define CMD_END		1
#define TIMEOUT		1
#define RSP_END		1
#define IN_PROGRESS	1

//about SDIDCON Register
#define SDIDCON_INT_PRD_OFFSET	21
#define SDIDCON_TARSP_OFFSET	20
#define SDIDCON_RACMD_OFFSET	19
#define SDIDCON_BACMD_OFFSET	18
#define SDIDCON_BLK_MODE_OFFSET	17
#define SDIDCON_WIDE_BUS_OFFSET	16
#define SDIDCON_DMA_ENABLE_OFFSET 15
#define SDIDCON_STOP_OFFSET	14
#define SDIDCON_DAT_MODE_OFFSET	12
#define SDIDCON_BLK_NUM_OFFSET	0

#define EXA_2_CYCLE	0
#define MORE_CYCLE	1
#define AFTER_DM_SET	0
#define AFTER_RSP_RCV	1
#define AFTER_CMD_SNT	1
#define STREAM_DATA	0
#define BLOCK_DATA	1
#define STD_BUS		0
#define WIDE_BUS	1
#define DMA_DISABLE	0
#define DMA_ENABLE	1
#define STOP_NORMAL	0
#define STOP_FORCE	1
#define READY		0
#define BUSY_CHK_START	1
#define DATA_RCV_START	2
#define DATA_TRA_START	3

//about SDIDCNT register
#define SDIDCNT_BLK_NUM_CNT_OFFSET 12
#define SDIDCNT_BLK_CNT_OFFSET	   0

//about SDIDSTA	register
#define SDIDSTA_R_WAITREQ_OFFSET	10
#define SDIDSTA_INT_DET_OFFSET		9
#define SDIDSTA_FF_FAIL_OFFSET		8
#define SDIDSTA_CRC_STA_OFFSET		7
#define SDIDSTA_DAT_CRC_OFFSET		6
#define SDIDSTA_DAT_TOUT_OFFSET		5
#define SDIDSTA_DAT_FIN_OFFSET		4
#define SDIDSTA_BUSY_FIN_OFFSET		3
#define SDIDSTA_SBIT_ERR_OFFSET		2
#define SDIDSTA_Tx_DAT_ON_OFFSET	1
#define SDIDSTA_Rx_DAT_ON_OFFSET	0
#define RWAIT_REQ	0
#define NO_RWAIT_REQ	1
#define INT_DET		1
#define FIFO_FAIL	1
#define CRC_STAT_FAIL	1
#define RCV_CRC_FAIL	1
#define TIME_OUT	1
#define DAT_FIN_DET	1
#define BUSY_FIN_DET	1
#define TX_IN_PRG	1
#define RX_IN_PRG	1

//about SDIFSTA register
#define SDIFSTA_TFDET_OFFSET	13
#define SDIFSTA_RFDET_OFFSET	12
#define SDIFSTA_TF_HALF_OFFSET	11
#define SDIFSTA_TF_EMPTY_OFFSET 10
#define SDIFSTA_RF_LAST_OFFSET	9
#define SDIFSTA_RF_FULL_OFFSET	8
#define SDIFSTA_RF_HALF_OFFSET	7
#define SDIFSTA_FFCNT_OFFSET	0

#define SDI_INT_RSPCRC		17
#define SDI_INT_CMDSENT		16
#define SDI_INT_CMDTOUT		15
#define SDI_INT_RSPEND		14
#define SDI_INT_RWAITREQ	13
#define SDI_INT_IOINTDET	12
#define SDI_INT_FFFAIL		11
#define SDI_INT_CRCSTA		10
#define SDI_INT_DATCRC		9
#define SDI_INT_DATTOUT		8
#define SDI_INT_DATFIN		7
#define SDI_INT_BUSYFIN		6
#define SDI_INT_SBITERR		5
#define SDI_INT_TFHALF		4
#define SDI_INT_TFEMPTY		3
#define SDI_INT_RFLAST		2
#define SDI_INT_RFFULL		1
#define SDI_INT_RFHALF		0

struct CID_struct
{
	unsigned char MID;
	unsigned short OID;
	unsigned char PNM[5];
	unsigned char PRV;
	unsigned int PSN;
	unsigned short MDT;
	unsigned char CRC_1;
};

struct CSD_register_struct
{
	unsigned char CSD_STRUCTURE;
	unsigned char TAAC;
	unsigned char NSAC;
	unsigned char TRAN_SPEED;
	unsigned short CCC;
	unsigned char READ_BL_LEN;
	unsigned char READ_BL_PARTIAL;
	unsigned char WRITE_BLK_MISALIGN;
	unsigned char READ_BLK_MISALIGN;
	unsigned char DSR_IMP;
	unsigned short C_SIZE;
	unsigned char VDD_R_CURR_MIN;
	unsigned char VDD_R_CURR_MAX;
	unsigned char VDD_W_CURR_MIN;
	unsigned char VDD_W_CURR_MAX;
	unsigned char C_SIZE_MULT;
	unsigned char ERASE_BLK_EN;
	unsigned char SECTOR_SIZE;
	unsigned char WP_GRP_SIZE;
	unsigned char WP_GRP_ENABLE;
	unsigned char R2W_FACTOR;
	unsigned char WRITE_BL_LEN;
	unsigned char WRITE_BL_PARTIAL;
	unsigned char FILE_FORMAT_GRP;
	unsigned char COPY;
	unsigned char PERM_WRITE_PROTECT;
	unsigned char TMP_WRITE_PROTECT;
	unsigned char FILE_FORMAT;
	unsigned char CRC;
};

#define IDEL_STATE	0
#define READY_STATE	1
#define IDENT_STATE	2
#define STBY_STATE	3
#define TRAN_STATE	4
#define DATA_STATE	5
#define RCV_STATE	6
#define PRG_STATE	7
#define DIS_STATE	8


#endif


